This invention relates to a method of forming a fine electrode on a semiconductor substrate. The method is particularly suitable for forming a so-called T-shaped gate electrode of a heterojunction field-effect transistor (FET) with a very short gate length.
Heterojunction FETs are known as low-noise transistors and have been used, for example, in parabolic antennas for receiving satellite broadcast. Recently there is a demand for further improvements in the low-noise characteristics of FETs.
In general, for improving the low-noise characteristics of a FET in high-frequency bands such as microwave bands it is effective to shorten the gate length. However, shortening of the gate length leads to narrowing of the cross-sectional area of the gate and hence causes an increase in a parasitic resistance in the gate region in the direction of the high-frequency wave propagation. Such a resistance is called gate resistance. If the gate resistance increases, the high-frequency signal gain of the FET decreases.
In recent heterojunction FETs, a T-shaped gate structure is employed in order to shorten the gate length and decrease the gate resistance. In this gate structure, the gate electrode is T-shaped in cross section. The stem part of the T-shaped gate electrode stands on the substrate so that the arm part extends above the substrate. The gate length is determined by the width of the stem part. For further improvements in the low-noise characteristics of heterojunction FETs it is desired to decrease the width of the stem part of the T-shaped gate electrode.
Electron beam lithography is useful for defining very fine gate electrode patterns, but the resolution of electron beam lithography is limited at about 0.1 .mu.m. On the other hand, it is desired to form a T-shaped gate electrode shorter than 0.1 .mu.m in gate length. To accomplish this desire by using electron beam lithography, some special techniques are required.
In the accompanying drawings, FIGS. 6(A) to 6(F) illustrate a recently developed process for forming a T-shaped gate electrode by which the gate length is shortened to the extent of about 0.07 .mu.m.
Referring to FIG. 6(A), on a GaAs substrate 50 an insulating film 52 such as a silicon dioxide film or a silicon nitride film is formed, and a resist film 54 (will be referred to as EB resist film) for electron beam lithography is formed on the insulating film 52. In a region for forming a gate electrode, a window 56 is opened in the resist film 54 by electron beam exposure and subsequent development. The width D of the window 56 is 0.1 .mu.m.
Next, as shown in FIG. 6(B), a relatively thick resist film 58 (will be referred to as UV resist film) for ultraviolet ray lithography is formed over the entire area of the EB resist film 54 including the opening 56. At the interface between the UV resist film 58 and the already developed EB resist film 54, chemical reactions take place to form an intermediate layer 60 which differs in chemical composition from both the EB resist film 54 and the UV resist film 58. In the window 56 in the EB resist film 54, the intermediate layer 60 provides a sidewall. The thickness of the intermediate layer 60 is about 0.015 .mu.m.
Referring to FIG. 6(C), a window 62 for a T-shaped gate electrode is formed in the UV resist film 58 by a conventional image reversal method which includes the following process steps. It is assumed that the UV resist film 58 is a positive resist film. First, the UV resist film 58 is exposed to UV rays except in the area for the window 62. In the exposed region the UV resist film 58 becomes soluble in a developer solution (an alkali solution). Then, ammonia gas is applied to the UV resist film over the entire area. In the region exposed to UV rays, the resist film 58 reacts with ammonia gas and gradually becomes insensitive to UV rays and insoluble in developer solutions. Since the reaction starts on the surface of the UV resist film 58 and gradually proceeds in the film thickness direction, the extent of the changes in the sensitivity and solubility of the UV resist film becomes smaller as the depth from the film surface increases. Next, the whole area of the UV resist film 58 is exposed to UV rays. As a result, the UV resist film becomes soluble in a developer solution only in the area for forming the window 62. Then the UV resist film is developed to form the window 62. In cross section, the window 62 becomes inversely tapered toward the substrate because in the initially exposed region of the resist film 58 the extent of lowering of solubility by reaction with ammonia gas was inversely proportional to the depth from the UV resist film surface.
The intermediate layer 60 is insoluble in the developer solution and hence remains on the EB resist film 54. In the window 56 in the EB resist film 54, the intermediate layer 60 remains as a sidewall. Therefore, the effective width D' of the window 56 in FIG. 6(C) is narrower than the initial width D of the window 56 in FIG. 6(A). When D is 0.1 .mu.m and the thickness of the intermediate layer 60 is about 0.015 .mu.m, D' becomes about 0.07 .mu.m.
Next, as shown in FIG. 6(D), a window 66 is opened in the insulating film 52 under the window 56 in the EB resist film 54 by dry etching. Furthermore, under the window 66, a recess 68 is formed in the GaAs substrate 50 by dry etching. In these dry etching processes the intermediate layer 60 serves as an etch mask. The recess 68 in the substrate serves the purpose of reducing the unfavorable influences of a surface depletion layer right beneath the gate electrode.
Referring to FIG. 6(E), a gate electrode metal 70 such as, for example, WSi is deposited on the UV resist film 58 by directional sputtering. In the window 62 in the resist film 58, the metal 70 deposits on the intermediate layer 60, fills the window 56 in the resist film 54 and reaches the bottom of the recess 68 in the substrate through the window 66 in the insulating film 52. The metal film 70 deposited in the window 62 forms a T-shaped gate electrode. Since the cross section of the window 62 is tapered upward, the cross section of the metal film 70 deposited on the intermediate layer 70 is tapered upward. This is favorable for planarization of an interlayer insulator film (not shown) formed over the gate electrode.
After that, the UV resist film 58 is removed together with the overlying metal film 70 by a lift-off technique, and the intermediate layer 60 and the EB resist film 54 are removed. FIG. 6(F) shows the T-shaped gate electrode 70 formed by the above-described process. With this gate electrode, the gate length L is equal to the width D' of the opening 56 in FIG. 6(C). That is, by this process the gate length L is shortened to the extent of about 0.07 .mu.m by using the intermediate layer 60 as a sidewall in the opening 56 for defining the base part of the gate electrode.
However, the above-described process is not fully satisfactory for several reasons. First, the gate length cannot be made shorter than about 0.07 .mu.m because the intermediate layer 60 does not become thicker than about 0.015 .mu.m and undergoes etching when the insulating film 52 and the substrate are etched to form the window 66 and the recess 68. Second, it is difficult to accurately control the gate length because the composition and thickness of the intermediate layer 60 depend on many factors in the reaction between an EB resist and a UV resist. In the case of mass production, reproducibility of the intermediate layer will not be good, and therefore the yield of the aimed gate electrode will be insufficient.